This invention relates to electronic circuits, and in particular to sample-and-hold circuits.
Sample-and-hold (S/H) electronic circuits are commonly used in or in combination with analog-to-digital converters (ADCs), sigma-delta modulators, and other electronic devices. The sampling (or tracking) and holding of the value of an input signal is usually performed by a capacitor, which is usually disconnected (switched) from the input signal during the hold period.
FIG. 1A schematically depicts a conventional S/H circuit 100 in the sampling phase, and FIG. 1B schematically depicts the conventional S/H circuit 100 in the holding phase. As shown in FIGS. 1A, 1B, the circuit 100 has an input driver amplifier 110 that produces an output signal connected through a controllable switch 120 to a sampling capacitor 130, which can be discharged through a controllable switch 140. During the sampling phase (FIG. 1A), the switch 120 is closed and the switch 140 is open, and so the sampling capacitor 130 is connected on one side to the input driver, which is depicted as an operational amplifier having direct (+) and inverting (−) inputs, and on the other side to ground, or earth, or another suitable reference potential. During the holding phase (FIG. 1B), the switch 120 is open, and so the sampling capacitor is disconnected from the driver 110. The sampling capacitor is typically discharged during the holding phase or is reset (discharged) before the start of the next sampling phase, and such operation is represented by closure of the switch 140.
Successive-approximation register ADCs (SAR-ADCs) with capacitor-based internal digital-to-analog converters (DACs) have recently regained interest, mainly because of their power efficiency and the good capacitor-matching possible in deep submicron integrated circuit fabrication processes. This type of ADC combines a S/H circuit, which is sometimes also called a track-and-hold (T/H) circuit with the internal DAC. A typical conversion starts with charging the sampling capacitor to the input voltage, followed by a successive approximation process, in which the charge on the sampling capacitor is gradually driven to zero. SAR-ADCs, as well as sigma-delta ADCs and other devices using S/H circuits are described in U.S. Patent Application Publications No. US 2011/0241912 A1 by Doris et al. and No. US 2011/0200070 A1 by Makinwa et al., for example.
A problem with the conventional S/H circuit 100 and devices, such as SAR-ADCs, that include conventional S/H circuits is that the driver amplifier 110 needs to supply substantial current to charge up the sampling capacitor 130 when the sampling capacitor is switched to the signal that is to be sampled, i.e., the amplifier output signal. If the driver amplifier 110 is unable to provide the high current, the driver output signal will take time to slew to its proper value. Such time delay can be unacceptable in a wide variety of applications of S/H circuits.
Some approaches to solving that problem are known. For example, U.S. Patent Application Publication No. US 2008/0024351 A1 by A. Gupta et al. and Section 3.2 of A. Gupta, “Design Techniques for Low Noise and High Speed A/D Converters”, Thesis for Master of Science, Texas A&M Univ. (2006) disclose S/H circuits that include pre-charge capacitors that store charge during the conversion (or holding) phase and that use the stored charge to load part, e.g., 90%, of the charge required by the sampling capacitor. Coarse and fine sampling phases are provided to ensure that the sampling capacitor settles fast.
International Publication WO 2011/036529 A2 by O. Moldsvor et al. states that it discloses a circuit having an input, two or more sampling capacitors, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means for using a voltage across a sampling capacitor for processing in a conversion phase. The two sampling capacitors are operated in anti-phase such that the reset and sampling phases of one channel are performed during the period that the other channel is in the conversion (or holding) phase. Nevertheless, current spikes are still demanded from the driver amplifiers when the sampling capacitors are switched.
U.S. Pat. No. 5,617,093 to Klein states that it discloses a filter of a type that transfers charge packets through the filter that are proportional to the magnitude of periodic samples of an input signal. The filter's effective input capacitance is minimized by providing a supplemental source that charges the filter's input capacitor to a level approximately the same as the level that would be reached for the input signal. This can be expected to work only when the input frequency is much lower than the sampling rate, which is typically not the case in a S/H circuit for an ADC. In fact, the input capacitance is doubled when the input frequency is one-half the sampling frequency, which is undesirable in an ADC.